Static Power Estimation of CMOS Logic Blocks in Static Power Estimation of CMOS Logic Blocks in

This paper introduces a new approach to pattern dependent static power estimation in logic blocks, which are realized ‘on-the-fly’ in a library-free design environment. A static current model is first developed at the transistor level and then extended to the logic gate level and finally the logic block level. For varying transistors widths and input stimuli, the transistor level model has performed with good accuracy compared to SPICE for technologies ranging from 65nm down to 32nm. The gate level model is pattern dependent and deals with basic gates and complex gates. A transistor collapsing scheme was developed to achieve simpler structure leading to analytical models with high computational efficiency and good accuracy ranging from 0.1-5.4% for basic logic gates and 3.7-6.2% for complex gates. Using these static current estimation models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which the cells are generated and sized ‘on-the-fly’ driven by specification and targeted technology. Across several MCNC benchmarks, the estimation methodology proposed exhibits a worst case mean percentage error of 1.1% compared to SPICE. It also exhibits runtime that is on average 43 times faster than SPICE.